Errors are detected by comparing the
Errors are detected by comparing the output data against an error free reference. After error detection, the process is restarted so that only one error is accounted. The susceptibility is inferred by the ratio between injected events and detected errors: = 100×errors÷events%.
Error rates are obtained by simulation with the addition of the susceptibility evaluation elements of Fig. 4. Area results are obtained by synthesis, without the susceptibility evaluation elements. Preliminary error rates shall be acquired for a reference description with no mitigation. The evaluation process is carried out by comparing the error rates and respective area for different tolerant implementations based on the reference description.
Susceptibility evaluation of the JPEG-LS descriptions A spreadsheet was used to guide the addressing of the event distribution along the different signals declared in the VHDL code, which were classified as: array, FIFO, line-buffer, combinatorial and sequential signals. The classification was used for the evaluation of the susceptibility related to each group of injection points. Even though there are many layers in combinatorial logic necessary to implement the Fluorescein TSA algorithm, only the signals declared in the application description were exploited as target for SET injection. This is a limiting factor for the injection model accuracy (See discussion in Section 4.2). One-hot encoding was applied to the finite-state machine (FSM) and, in case of an illegal state (When Others), the process was forced to a default condition with a general reinitialization of variables. The data acquisition point for the detection of errors, caused by event injection, was placed at the Golomb/Run encoder output, as shown in the block diagram of Fig. 1. The Simplified JPEG-LS description of Ref.  was evaluated with a random test image, Rand 1 in Fig. 5, to increase and scatter the number of contexts. In the present study, the addition of the encoder to the JPEG-LS standard Reference description exposed the low compression rates associated with the Rand 1 image model. Therefore, in order to avoid FIFO 1 overflow, a smoother (strongly correlated) test image, Rand 2 in Fig. 5, was employed. The differences between the Simplified description  and the JPEG-LS standard Reference description, used in the present work, are listed in Table 1.
Synthesis results for the reference and the tolerant JPEG-LS descriptions Synthesis evaluation was performed using the Synplify Pro E-2010.09A-1 tool. The results for the Reference description, in Table 7, indicated the Axcelerator's RAM size limitations, which would without a doubt impair the mitigation strategy. Table 7 includes the respective power estimate for the AX1000 (at a 50 MHz clock and a 3.3 V I/O voltage), whose consumption is higher than the ProASIC3′s one. The results for the Tolerant description are presented in Table 8. In comparison with Table 7, the rise in the number of logic cells was 27% for the ProASIC and 43% for the Axcelerator. The reason is that only the registers were protected by TMR and a significant part of the operations were implemented in combinatorial logic. Because of AX1000′s RAM limitation, the respective line-buffer was kept unprotected. Thus, the erate estimate in the first line of Table 5 rose significantly to 45%. It is also observed that the increase in the area due to mitigation was proportionally smaller for the ProASIC FPGA. The reason can be attributed to a different resource utilization optimization because of the FPGA's internal architecture (ProASICs are based on more versatile logic cells). To emphasize the differences in the synthesis processing a 4 bit Gray code counter was employed and the results are listed in Table 9. The higher area resource requirement, because of the use of TMR, is evident (3.5 times) for the Axcelerator, but smaller (<2.5 times) for the ProASIC. In Ref. , synthesis was basically employed to verify the area overhead due to mitigation, without any concern about device area constraints. In this work, device area limitation had to be considered in the tradeoff analysis and the results pointed out the viability of implementing the tolerant JPEG-LS compression in medium-size flash or antifuse FPGAs. Except for the Axcelerator's RAM, there is enough room to include additional functions like data packing and even for improving the design hardening. To overcome the unacceptable rise in the susceptibility and to avoid a more expensive AX2000, which would be underused, the line-buffer could be implemented in a FIFO outside the AX1000. To protect a 16k×9 bit FIFO with Hamming code the remaining AX1000′s RAM blocks would be enough to store the respective parity bits.