Archives

  • 2018-07
  • 2018-10
  • 2018-11
  • 2019-04
  • 2019-05
  • 2019-06
  • 2019-07
  • 2019-08
  • 2019-09
  • 2019-10
  • 2019-11
  • 2019-12
  • 2020-01
  • 2020-02
  • 2020-03
  • 2020-04
  • 2020-05
  • 2020-06
  • 2020-07
  • 2020-08
  • 2020-09
  • 2020-10
  • 2020-11
  • 2020-12
  • 2021-01
  • 2021-02
  • 2021-03
  • 2021-04
  • 2021-05
  • 2021-06
  • 2021-07
  • 2021-08
  • 2021-09
  • 2021-10
  • 2021-11
  • 2021-12
  • 2022-01
  • 2022-02
  • 2022-03
  • 2022-04
  • 2022-05
  • 2022-06
  • 2022-07
  • 2022-08
  • 2022-09
  • 2022-10
  • 2022-11
  • 2022-12
  • 2023-01
  • 2023-02
  • 2023-03
  • 2023-04
  • 2023-05
  • 2023-06
  • 2023-07
  • 2023-08
  • 2023-09
  • 2023-10
  • 2023-11
  • 2023-12
  • 2024-01
  • 2024-02
  • 2024-03
  • 2024-04
  • Besides studying a solution for an onboard

    2020-07-30

    Besides studying a solution for an onboard tolerant system, this work evaluates the effectiveness of the soft-error mitigation strategy through simulation-based analysis of the VHDL (Very high-speed integrated circuits Hardware Description Language) code. The system employs the JPEG-LS image Sephin1 standard on account of the good tradeoff between compression rate, image loss and area requirements attained with a SRAM-based FPGA [15]. The moderate area and memory requirements made it possible to consider future use of two FPGA types: a flash ProASIC3 or an antifuse Axcelerator. These are medium-size devices with a lower susceptibility to the radiation effects than that of SRAM-based FPGAs [16], [17], and with enough room to house the hole compression system. The low memory demanded by predictive-differential compression methods, like JPEG-LS, is one important advantage over transform-based ones [15], but one drawback is that a single soft error can corrupt part of a packed data block [18]. Therefore, the addition of soft-error mitigation is mandatory and widespread TMR (Triple Modular Redundancy) and Hamming EDAC (Error Detection And Correction) were selected as fault mitigation techniques, taking into account an LEO space radiation environment. An upgraded version of the simulation-based method, described in Ref. [19], was employed to analyze the soft-error susceptibility of the JPEG-LS VHDL code. The susceptibility analysis method is based on random SET and SEU injection, and resulting error rate evaluation. In Ref. [19], a simplified JPEG-LS description (Regular mode only, without encoding process), handling a small test image (200 pixels per line), was submitted to a partial hardening analysis to verify the coherence of the proposed method and estimates. The paper is organized as follows. Section 2 gives a brief presentation of the JPEG-LS algorithm and respective hardware implementation. In Section 3 the fault injection model and the simulation-based susceptibility analysis method are reviewed. Section 4 provides a discussion on the susceptibility evaluation results for a reference description and for a tolerant description of the JPEG-LS compression algorithm. The synthesis results are presented in Section 5, scrubbing process is included and evaluated in Section 6 and the conclusions are exposed in Section 7.
    JPEG-LS standard JPEG-LS international standard defines a set of lossless or near-lossless compression methods for the coding of still images [20]. The Low Complexity Lossless Compression for Images (LOCO-I) algorithm [21] is the basis of the JPEG-LS standard. A block diagram of LOCO-I algorithm is represented in Fig. 1. An important control parameter of this algorithm, named NEAR, defines the amount of near-lossless compression (NEAR=0 for lossless compression). The modeling approach is based on the notion of “contexts”, where, for each sample x, a context is determined by the gradients of the neighboring reconstructed samples a, b, c, and d. At the flat regions of the image, if the context estimates that neighboring samples are nearly identical, then the processing is switched to Run mode, otherwise the Regular mode is maintained.